VS1005g Datasheet
10
To compensate the FM signals’s level changes an analog gain control is added.
FM gain settings
Gain bits Gain
000 11dB
100 14dB
010 17dB
001 20dB
VS1005 PERIPHERALS AND REGISTERS
Example values to configure analog modules are given in the table. Here the VCO’s control bits
are ignored.
Analog Control Register Examples
Address
Register Min Gain Max Gain
0xFECB ANA_CF1 0x0000
0x0000
0xFECC ANA_CF0 0x0003
0x0003
0xFED2 ANA_CF2 0x03CB
0x03CB
0xFED3 ANA_CF3 0x2000
0x23F0
10.17.2 Configuring FM Demodulator
PR
EL
IM
Reg
0xFE40
0xFE41
0xFE42
0xFE43
0xFE44
0xFE45
0xFE4E
0xFE4F
0xFE50
0xFE51
0xFE52
0xFE53
0xFE5B
Type
r/w
r/w
r/w
r/w
r/w
r/w
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Version: 0.2, 2012-03-16
The FM demodulator has several configuration registers that must be initialized in order to
receive an FM channel. FM demodulator’s control and data registers are listed in next table.
FM Control and Data Registers
Abbrev
Description
FM_CF
FM demodulator control register
AD_CF
AD filter configuration register
FMPLL_LO
FM PLL carrier frequency register bits [15:0]
FMPLL_HI
FM PLL carrier frequency register bits [28:16]
FMCCF_LO
Carrier center frequency register bits [15:0]
FMCCF_HI[10:0]
Carrier center frequency register bits [26:16]
DEC6_LEFT_LSB[15:14]
FM filter left channel bits [1:0]
DEC6_LEFT
FM filter left channel bits [17:2]
DEC6_RIGHT_LSB[15:14] FM filter right channel bits [1:0]
DEC6_RIGHT
FM filter right channel bits [17:2]
RDS_DATA[15:0]
FM RDS data register
RDS_CHK[12:0]
FM RDS checkwork and block status
FM_PHSCL
FM I/Q phase error scaling factor
FM_CF register is a configuration register which is used to select demodulator operation modes.
The FMCCF_HI and FMCCF_LO are used to tune FM receiver to a certain channel. The FM-
PLL_HI and FMPLL_LO registers are used to match xtal frequency to the stereo subcarrier
frequency (38kHz).
IN
AR
86
Y
ETC [ ETC ]
