VS1005g Datasheet
7
VS1005 GENERAL DESCRIPTION
7 VS1005 General Description
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Version: 0.2, 2012-03-16
Figure 7: VS1005 External Interfaces
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Vs1005 architecture is based on VS_DSP core. VS_DSP core architecture is described in
VS_DSP User’s Manual. Chip is powered with internal regulator which provides voltages for
three separate power domains. The core and periphery I/O power domains can be driven off
separately, allowing simple I/O interfacing and minimizing power consumption. RTC has its own
power supply which enables the RTC usage when the rest of the chip is powered down. RTC
also includes a small backup ram. Vs1005 has two clock domains which are clocked by PLL.
Analog interfaces are clocked with a XTAL clock but the dsp, digital intarfaces and memories
are clocked with a multiplied clock. Vs1005 external interfaces are shown in figure 7.
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