VS1005g Datasheet
5
Pin Name
Analog Line input 1
Analog Line input 2
Analog Line input 1
Analog Line input 2
Digital DA/AD Clock
Digital DAC Right
Digital DAC Left
Digital ADC 1
Digital ADC 2
Digital ADC 3
TMS
TDI
TDO
TCK
DBGREQ
PACKAGE AND PIN DESCRIPTIONS
68
67
52
32
33
53
55
51
31
32
33
34
35
AI
AI
DO
DO
DO
DI
DI
DI
DI
DI
DO
DI
DO
Pin type descriptions:
Type
DI
DO
DIO
AI
AO
AIO
Description
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
Analog input
Analog output
Analog input/output
PR
EL
IM
5.3.1
PCB Layout Recommendations
Version: 0.2, 2012-03-16
Package bottom plate is a ground net and it is connected to ground network in PCB.
NOTE: Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. At
power-up all GPIO is three stated and current leakage from IOVDD is cut. Outputs that are
three-statable should only be pulled high or low to ensure signals at power-up and in standby.
The following recommendations should be followed to ensure reliable operation.
•
Analog power nets that are connected to regulator APWR/CPWR output should have
bypass capasitors.
•
USBP and USBN traces should be kept within 2mm of each other and with preferred
length of 20-30mm (max 75mm). A solid ground plane is preferred under USBP and
USBN traces.
•
USBP and USBN traces should be very close to same length, drawn together and their
characteristic differential impedance 90 Ohms
•
No vias are allowed in USBP or USBN traces, only 45 degree angles should be used.
•
USBP and USBN traces should be isolated from all other signal traces.
•
RF_P and RF_N traces should be isolated from all other signal traces.
IN
AR
Alternate analog input pin for Line input 1
Alternate analog input pin for Line input 2
Digital DA/AD clock output, xtal/2/4
DAC right channel digital output, xtal/2
DAC left channel digital output, xtal/2
Digital ADC 1 input, xtal/2
Digital ADC 2 input, xtal/2
Digital ADC 3 input, xtal/2
Jtag Test Mode Select
Jtag Test Data In
Jtag Test Data Out
Jtag Test Clock
Hardware debug state pin
Type
APWR
APWR1V8
RTCPWR
DGND
CPWR
IOPWR
Description
Analog power supply pin or ground
Analog power supply pin, 1.8V
Real time clock power supply pin, 1.8V
Core or I/O ground pin
Core power supply pin
I/O power supply pin
Alternate pin functions in vs1005 package
LFGA Pin Type
Function
Pin
71
AI
Alternate analog input pin for Line input 1
70
AI
Alternate analog input pin for Line input 2
Y
18
ETC [ ETC ]
