CD-700, VCXO Based PLL
Vd
VDD
0
−π
+π
Relative
Phase (θe)
VDD/2
0V
Gain Slope = VDD/ 2
π
Figure 5, Open Loop Phase Detector Transfer Curve
Recovered Clock and Data Alignment Outputs
The CD-700 is designed to recover an imbedded clock from an NRZ data signal and retime it with a data
pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and
the outputs are taken off Pin 9, RCLK, and Pin 10, RDATA. Under locked conditions, the falling edge of
RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock cycle delay between DATAIN and
RDATA. Figure 6 shows the relationship between the DATAIN, CLKIN, RDATA and RCLK.
Data1
Data In
DATAIN
Clock In
CLKIN
Recoverd Data
RDATA
Data1
Recoverd Clock
RCLK
Figure 6, Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at twice
the baud rate.
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is
normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no
detected DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the
CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 16) is switched
to an internal voltage which centers OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS
automatically closes the op amp feedback which means the op-amp is a unity gain buffer and will produce
a DC voltage equal to the +op amp voltage (pin 15), usually VDD/2.
Vectron International • 166 Glover Avenue, Norwalk, CT 06856 • Tel: 1-88-VECTRON-1• http://www.vectron.com
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