EAGLE
PRELIMINARY
Ver 1.3
- Sync. Timing Generation
Figure 3-13 shows the timing relationship of sync. signals,: Horizontal Total, Sync Start (End), Active Start (End),
Vertical Total, Sync Start (End) and Active Start (End) for 640 X 480 resolution configuration.
HSYNC and VSYNC signals are active low by default but the active polarity of these signals can be modified by setting
the CRT Control Register bit[5:4]. Horizontal and Vertical Active signals are active high signals.
Figure 3-13 CRTC Horizontal, Vertical Sync / Active Signal Timing
- Color Bar Test Pattern Generation Block
When CRT Control Register bit[1:0] is set to “01”, Color Bar Test Pattern Generation block is activated while Request
Generation, Address Generation and FIFO Control blocks are inactive. Color Bar Pattern is generated in the order: black,
white, yellow, cyan, green, purple, red, and blue (from left to right). These colors are uniformly distributed regardless of their
resolution. If the size of Active block is not a multiple of 8, the right side of the screen output can be in black color.
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
96
ETC [ ETC ]
