EAGLE
PRELIMINARY
Ver 1.3
- Address Generation
The Address Generation block generates memory read request address for screen refresh.
Memory read request address is generated by adding the CRT Base Address (programmed by user) to address offset with
reference to the corresponding internal mode.
- FIFO / Request Control
The FIFO control block controls the read request, write and read pointer of internal FIFO. Read request, write and read
pointer is reset at the end of Horizontal Active duration.
FIFO Control block has two clock domain. One is system clock domain that is used for writing frame memory data to FIFO.
The other is video (Dot) clock domain used for displaying FIFO Data on screen.
The read/write data bus width for FIFO is 32bit. <16 or 24> bit per Pixel (RGB) color mode can be configured by setting
the Control register bit[16] with (5:6:5 Format) color mode as the initial mode in RGB 16 bit.
For RGB 16 bit(5:6:5 Format) color mode, one FIFO read/write operation handles 2 Pixels with the lower 16Bits ([15:0])
out of 32 bits first being displayed, followed by upper 16 bits ([31:16]). 1 Pixel resolution is 16bits, R value[15:11], G
value[10:5] and B value[4:0]. When RGB 24 bit (8:8:8 Format) Color mode is chosen by setting a ‘1’ to Control register
bit[16], one FIFO read/write operation only handles 1 Pixel of 32 bits, composed of { Dummy 8 Bit[31:24], R[23:16],
G[15:8], B[7:0] }.
The frame memory video data signal request is generated by checking the FIFO read pointer at every active period line.
When the read pointer value is “00”, “11”, “01” and “10”, the request signal will be generated when FIFO reaches half-
full, quadrant-full and octant-full status. In the case of CRT Control Register[18:17] bit set to “00” or “11”, “01”, and “10”,
FIFO will be fill-up to full, half-full, and quadrant-full states at every line of Horizontal HSYNC. Inter FIFO size is 256 x 32.
Figure 3-12 CRT FIFO Control Block – RGB 16 Bit(5:6:5) Format Operation
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
94
ETC [ ETC ]
