Ver 1.3
PRELIMINARY
EAGLE
3.5.4 Interrupt Enable Register (INTEN)
This register enables and disables each interrupt. Interrupt is disabled by setting a ‘0’ to the corresponding register bit and a
value ‘1’ enables the interrupt. Setting an INTEN register bit to ‘0’ inhibits the corresponding interrupt source from
generating an interrupt to the AE32000C core. Table below shows the interrupt source of each INTEN register bit.. Caution
should be taken when configuring this register.
Address : FFE0 0C0Ch
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
External IRQ7 (Lowest Priority)
TWI interrupt or H.264 IRQ1
External IRQ6
External IRQ5
GUN interrupt
JPEG Decoding End IRQ
JPEG FIFO Fill Request IRQ
External IRQ4
Sound Mixer interrupt
I2S interrupt
Default Value
0000 0000h
SDC interrupt
UART Channel 3 interrupt or H.264 IRQ0
UART Channel 2 interrupt
SPI interrupt
USB device interrupt
NAND Flash Controller interrupt
Key Scan interrupt
CRT External Sync. Detect interrupt
USB host interrupt
Frame Vsync interrupt
External IRQ3
External IRQ2
UART Channel 1 interrupt
UART Channel 0 interrupt
Timer 3 interrupt
Timer 2 interrupt
DMA 1 interrupt
DMA 0 interrupt
External IRQ1
External IRQ0
Timer 1 interrupt
8
7
6
5
4
3
2
1
0
Timer 0 interrupt (Highest Priority)
73
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
