Ver 1.3
PRELIMINARY
EAGLE
3.4.8 GDMA Source Address Register (GDMASn)
This Register represents the origin address of Data (byte sort) to be transferred.
Address : FFE0 0824h/FFE0 0844h
Bit
31 : 0
R/W
R/W
Description
DMA Source Address A[31:0]
Default Value
0000 0000h
3.4.9 GDMA Destination Address Register (GDMADn)
This Register represents the target address of Data (byte sort) to be transferred.
Address : FFE0 0828h/FFE0 0848h
Bit
31 : 0
R/W
R/W
Description
DMA Destination Address A[31:0]
Default Value
0000 0000h
3.4.10 GDMA Transfer Count Register (GDMATn)
This Register represents the number of Data transfer of DMA controller.
Address : FFE0 082Ch/FFE0 084Ch
Bit
31 : 24
23 : 0
R/W
R
R/W
Description
Default Value
Reserved
-
DMA Transfer Count Register.
00 0000h
At every Data transfer, decremented by 1.
Also decremented by 1 in case of burst.
ex) 16burst * 32bit * 1(Count) = 64byte
3.4.11 GDMA Descriptor Table Address Register (GDMADTn)
When DMA controller is operating in Chain mode, it represents the address of Descriptor table.
Address : FFE0 0830h/FFE0 0850h
Bit
R/W
Description
Default Value
31:0
R/W
DMA Descriptor Table Address A[31:0]
0000 0000h
69
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
