EAGLE
PRELIMINARY
Ver 1.3
3.5 Interrupt Controller
The interrupt controller in Eagle has 32 interrupt channels. The interrupt controller has the responsibility of forwarding an
interrupt request to the AE32000C core according to a fixed priority or user defined priority based on the mask bit of each
used or unused interrupt.
The 32 channels are divided into 24 internal interrupt channels and 8 external interrupt channels. There are up to five types
of interrupt latching configurations for external interrupt. This is done by setting the INTMOD register appropriately.
Interrupt controller ignores any internal or external interrupt requests if the corresponding channel of the interrupt resource
has been disabled in the INTEN register (INTEN bit is set to ‘0’). The interrupt controller will generate an interrupt if the
channel of the corresponding interrupt request is enabled. (INTEN bit is set to ‘1’). By default, the interrupts are not routed
to the AE32000C Core due to the masking of interrupt request signals. In order to generate an interrupt to AE32000C core,
the interrupt signals should be unmasked by configuring the INTMSK register. If an interrupt is requested to the AE32000C
core, the INTVEC register shall provide the interrupt vectors which contain the address of the requesting interrupt channel.
The status of the requesting interrupt will be reflected in the INTSTAT register. When the AE32000C core receives an
interrupt request, it will execute the ISR (Interrupt Service Routine) that belongs to the corresponding interrupt request.
When the ISR is completed, INTVECCLR register will be set to indicate the end of an interrupt request process.
The interrupt controller processes the interrupt with higher priority if there are more than one interrupt requests coming
from different interrupt channels at the same time. The interrupt controller may choose to ignore a new interrupt which
comes from the interrupt resource with pending interrupt request that has not completed the ISR. However, the interrupt
controller may process the new interrupt request if it has sufficient time to complete all ISRs
Even though the interrupt priority is fixed, user can adjust the order of internal interrupt priority by configuring the
INTMOD[31] bit and INPPRn register. For external interrupt with the same interrupt trigger mode, user can choose to adjust
the order of interrupt priority. The order of interrupt priority shall revert to the default priority by: a system reset, user
register write instruction or INTMOD[31] bit is set to ‘0’.
Figure 3-5 Structure of Interrupt Controller
Interrupt Controller Register Summary
Address
Register Name
Description
External Interrupt and Mode Select
Interrupt vector
Interrupt service clear
Interrupt Enable/Disable
Interrupt status
FFE0 0C00h External Interrupt Source & Mode Select Register (INTMOD)
FFE0 0C04h Interrupt Vector Register (INTVEC)
FFE0 0C08h Interrupt Vector Clear Register (INTVECCLR)
FFE0 0C0Ch Interrupt Enable Register (INTEN)
FFE0 0C10h Interrupt Status Register (INTSTAT)
FFE0 0C14h
~
Interrupt Priority Programmable Register (INPPRn)
Interrupt source Priority Program
FFE0 0C30h
Internal Interrupt source Trigger
mode Select
FFE0 0C34h Interrupt Trigger Mode Programmable Register (IRQTRMD)
FFE0 0C38h Interrupt Output Masking Register (INTMSK)
FFE0 0C40h MCU Core Handshake Register (INTHSMCU)
Interrupt request masking
Handshake with MCU core
Table 3-8 Interrupt Controller Registers Table
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CONFIDENTIAL
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