EAGLE
PRELIMINARY
Ver 1.3
3.5.5 Interrupt Status Register (INTSTAT)
This register shows the status of interrupt events. INTSTAT bit is set to ‘1’ when an interrupt event is detected. Upon
completion of ISR (Interrupt Service Routine), the corresponding INTSTAT bit shall change to ‘0’ when interrupt vector is
cleared. Information of an interrupt occurrence and the source of that interrupt can be obtained by reading the INTSTAT
register.
Address : FFE0 0C10h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
R/W
R
Description
External IRQ7 (Lowest Priority)
TWI interrupt or H.264 IRQ1
External IRQ6
External IRQ5
GUN interrupt
JPEG Decoding End IRQ
JPEG FIFO Fill Request IRQ
External IRQ4
Sound Mixer interrupt
I2S interrupt
Default Value
0000 0000h
SDC interrupt
UART Channel 3 interrupt or H.264 IRQ0
UART Channel 2 interrupt
SPI interrupt
USB device interrupt
NAND Flash Controller interrupt
Key Scan interrupt
CRT External Sync. Detect interrupt
USB host interrupt
Frame Vsync interrupt
External IRQ3
External IRQ2
UART Channel 1 interrupt
UART Channel 0 interrupt
Timer 3 interrupt
8
7
6
Timer 2 interrupt
5
DMA 1 interrupt
4
DMA 0 interrupt
3
External IRQ1
2
External IRQ0
1
Timer 1 interrupt
0
Timer 0 interrupt (Highest Priority)
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
74
ETC [ ETC ]
