EAGLE
PRELIMINARY
Ver 1.3
3.4.7 GDMA Control Register (GDMACONn)
DMA Control Register includes DMA channel information about input selection, transfer mode and size of transferred data.
Each register is programmed by software before DMA channel is enabled. When DMA operation is completed, Run DMA
Operation flag is set to ‘0’.
Address : FFE0 0820h/FFE0 0840h
Bit
31: 25
24
R/W
R
R/W
Description
Default Value
Reserved
Run DMA Operation
0 : Cancels DMA Operation
-
0b
1 : Starts DMA Operation by S/W
23 : 19
18 : 16
R
R/W
Reserved
Channel 0
-
0b
Channel 1
DMA Request Source Selection
000 : External DREQx0
001 : I2S (CH0)
DMA Request Source Selection
000 : External DREQx1
001 : Nand Flash RX DREQx
010 : SDC DREQx
010 : SPI DREQx
011 : Reserved
011 : Reserved
100 : Reserved
1xx : DMA Channel 1 (SW)
101 : Nand Flash TX DREQx
11x : DMA Channel0 (SW)
Active DMA Chain Mode
0 : Direct Mode 1 : Chain Mode
Protection and access information(AMBA Protection control)
bit 12 : Privileged or User
15
R
0b
0b
14 : 12
R/W
bit 13 : Bufferable or not bufferable
bit 14 : Cacheable or not cacheable
Lock(AMBA Lock)
0: unLock 1 : Lock
DMA Transfer Count Mode
0 : Reference Count
11
10
R/W
R/W
0b
0b
1 : not used (unlimited transfer)
9 : 8
7 : 6
R/W
R/W
DMA Burst Size
00 : No burst
0b
0b
01 : 4 beat incrementing burst
10 : 8 beat incrementing burst
11 : 16 beat incrementing burst
Direction of DMA Source Address
00 : Fixed Address :Do not change address
01 : Reserved
10 : Increment
11 : Decrement
Increase address
Decrease address
5 : 4
3 : 2
R/W
R/W
Direction of DMA Destination Address
0b
0b
00 : Fixed Address
10 : Increment
01 : Reserved
11 : Decrement
Data Size for Transfer
00 : 8bit Transfer using 1Byte size
01 : 16bit Transfer using 1Half word size
10 : 32bit Transfer using 1Word size
11 : Reserved
1 : 0
R
Reserved
-
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
68
ETC [ ETC ]
