Ver 1.3
PRELIMINARY
EAGLE
Register Name
Address
Description
MEMCON1
MEMCON2
MEMCON3
MEMCON4
FFE0 0404h
FFE0 0408h
FFE0 040Ch
FFE0 0410h
Memory Bank 1 Control Register
Memory Bank 2 Control Register
Memory Bank 3 Control Register
Memory Bank 4 Control Register
SRAM and ROM can be used in Memory Bank 1 to 4. Bank 1 to Bank 4 have the same configuration register as shown in
the register below.
SRAM, ROM Mode
Bit
31 : 16
15 : 14
R/W
R
R/W
Description
Default Value
Reserved
Address Set-up before CSx
-
11b
00 : 0 Clock
10 : 2 Clock
01 : 1 Clock
11 : 4 Clock
13 : 12
11 : 8
R/W
R/W
Chip Selection Set-up RDx / WRx
11b
00 : 0 Clock
10 : 2 Clock
01 : 1 Clock
11 : 4 Clock
Access Cycle
0000 : 1 Clock
0010 : 3 Clock
0100 : 6 Clock
0110 : 10 Clock
1000 : 14 Clock
1010 : 18 Clock
1100 : 22 Clock
1110 : 26 Clock
1111b
0001 : 2 Clock
0011 : 4 Clock
0101 : 8 Clock
0111 : 12 Clock
1001 : 16 Clock
1011 : 20 Clock
1101 : 24 Clock
1111 : 30 Clock
7 : 6
5 : 4
3
R/W
R/W
R/W
Chip Selection Hold on RDx / WRx
11b
11b
0b
00 : 0 Clock
10 : 2 Clock
01 : 1 Clock
11 : 4 Clock
Address Holding Time after CSx
00 : 0 Clock
10 : 2 Clock
01 : 1 Clock
11 : 4 Clock
This bit indicates the use of SRAM memory UBEx/LBEx pin for Bank1
to Bank 4.
0 : Not using UBEx/LBEx
1 : Using UBEx/LBEx for 16bit SRAM
2
R/W
R/W
This bit determines the WAIT status of Bank 1 to Bank 4.
0 : WAIT Inactivation
1 : WAIT Activation
These bits determine the data bus width for Bank 1 to Bank 4.
0b
1 : 0
01b
00 : 8 bit
01 : 16 bit
10 : 32 bit
11 : Reserved
< Register Description >
(1) Bit[15:14] : This field identifies the number of clock cycles to set up Chip Select signal after Address signal becomes
available. (Refer to tCSS as shown in Figure 3.1)
(2) Bit[13:12] : This field identifies the number of clock cycles that Chip select signal should remain enabled prior to the
deassertion of RDx / WRx signal. (Refer to tOES in Figure 3.1)
(3) Bit[11:8] : The value of RDx / WRx signal should be maintained for the number of clock cycles identified by this field
(Access Time). (Refer to tACC in Figure 3.1)
(4) Bit[7:6] : This field identifies the number of clock cycles that RDx/WRx signal should remain deactivated prior to the
deactivation of Chip Select signal. (Refer to tOEH in Figure 3.1)
(5) Bit[5:4] : Chip Select signal shall remain disabled for the number of clock cycles (Hold Time) as identified by this field
prior to the end of Address signal. (Refer to tCSH in Figure 3.1)
(6) Bit[3] : This bit is cleared to ‘0’ when an 8-bit SRAM is used with a 16-bit or 32-bit external data bus. Write Enable
signals of SRAM are connected to their respective BEx signal. If a 16-bit SRAM is used, this bit shall be set to ‘1’ and
the UBEx and LBEx signals of SRAM shall be connected to their corresponding BEx signals.
53
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
