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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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Ver 1.3  
PRELIMINARY  
EAGLE  
CS0x  
O
B
Bank 0 ROM Chip Select (Active Low)  
Chip Select bank 1(Active Low) or Programmable I/O [16]  
CS1x / GPIO[16]  
This signal can be configured as chip select signal of bank 1 for SRAM/ROM or  
programmable I/O port[16], as determined by pin mux control register.  
Chip Select bank 2(Active Low) or Programmable I/O [17]  
CS2x / GPIO[17]  
CS3x / GPIO[18]  
B
B
This signal can be configured as chip select signal of bank 2 for SRAM/ROM or  
programmable I/O port[17], as determined by pin mux control register.  
Chip Select bank 3(Active Low) or Programmable I/O [18]  
This signal can be configured as chip select signal of bank 3 for SRAM/ROM or  
programmable I/O port[18], as determined by pin mux control register.  
Chip Select bank 4 (Active Low) or SPI_SSx (Active Low) or Programmable I/O[19]  
CS4x / SPI_SSx / GPIO[19]  
B
This signal can be configured as chip select signal of bank4 for SRAM/ROM, select  
signal for SPI device or programmable I/O port[19], as determined by pin mux  
control register.  
CS5x  
RDx  
WRx  
O
O
O
Bank 5 SRAM/ROM/SDRAM Chip Select (Active Low)  
SRAM/ROM Read Strobe (Active Low)  
SRAM/ROM Write Strobe (Active Low)  
SD Card Data [1] or SPI Master Output Slave Input or DMA Ch.1 Acknowledge  
signal (Active Low) or Programmable I/O[103]  
SDCD_DATA[1] / SPI_MOSI /  
DMA_ACKx[1] / GPIO[103]  
B
B
B
B
B
B
B
This signal can be configured as data[1] of SD card, Master Output Slave Input  
(MOSI) signal of SPI, acknowledge signal of DMA Ch.1 (Active Low) or  
programmable I/O[103], as determined by pin mux control register.  
SD Card Data [0] or SPI Master Input Slave Output or DMA Ch.1 Request Strobe  
signal (Active Low) or Programmable I/O[102]]  
SDCD_DATA[0] / SPI_MISO /  
DMA_REQx[1] / GPIO[102]  
This signal can be configured as data[0] of SD card, Master Input Slave Output of  
SPI, request signal of DMA Channel 1 or programmable I/O port[102], as determined  
by Pin Mux Control Register.  
SD Card Clock or SPI Serial Clock or External Interrupt Source[4] or Programmable  
I/O[101]]  
SDCD_CLK / SPI_SCK /  
EXT_IRQ[4] / GPIO[101]  
This signal can be configured as clock signal of SD card, serial clock of SPI, external  
interrupt source[4] or programmable I/O[101], as determined by pin mux control  
register.  
SD Card Command signal or Wait signal (Active Low) or I2S Serial Data Input or  
Programmable I/O[100]  
SDCD_CMD / WAITx /  
I2S_SDI / GPIO[100]  
This signal can be configured as command signal of SD card, wait signal (Active  
Low), serial data input of I2S or programmable I/O[100], as determined by pin mux  
control register.  
SD Card Data[3] or Key Scan Line Output[2] or External Interrupt Source[7] or  
SRAM or ROM Byte Enable[3] (Active Low)  
SDCD_DATA[3] / KEY_OUT[2] /  
EXT_IRQ[7] / BEx[3]  
This signal can be configured as data[3] of SD card, line output[2] of key scan,  
external interrupt source[7] or byte enable[3] for SRAM or ROM when 32-bit bus  
width is used, as determined by pin mux control register.  
SD Card Data[2] or Key Scan Data Input[2] or External Interrupt Source[6] or  
SRAM or ROM Byte Enable[2] (Active Low)  
SDCD_DATA[2] / KEY_IN[2] /  
EXT_IRQ[6] / BEx[2]  
This signal can be configured as data[2] of SD card or data input[2] of key scan,  
external interrupt source[6] or byte enable[2] for SRAM or ROM when 32-bit bus  
width is used, as determined by pin mux control register.  
Nand Flash Memory Busy signal (Active Low) or Non-Maskable Interrupt or  
Programmable I/O[20]  
NDFL_BUSYx / NMIx / GPIO[20]  
This signal can be configured as busy signal of NAND flash memory (Active Low),  
non-maskable interrupt signal to CPU or programmable I/O[20], as determined by  
pin mux control register.  
25  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
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