Ver 1.3
PRELIMINARY
EAGLE
3.19.1.1 Tx/Rx Interrupt
By default, the Tx/Rx FIFO interrupt is generated for Tx FIFO when FIFO is completely empty and for Rx FIFO, interrupt
is generated when Rx FIFO reaches the Receiver FIFO Trigger Level (RFTL) .
In Rx, interrupts are generated if data does not reach the Receiver FIFO Trigger Level (RFTL) after a certain period of time
(4~5 frame). This informs the UART to start data processing even though the number of data received is less than the Rx
interrupt condition. When an error occurs in the received data, interrupt is also generated by setting UIEn[2] bit to ‘1’. To
obtain the information on the type of errors in received data, please refer to the descriptions of ULSTATn register. User
should take note that FIFO interrupt and Received Data Error Interrupt shares the same Rx interrupt. The flow chart below
gives an overview on Rx/Tx interrupt and data flow in UART.
Figure 3-36 UART Rx/Tx Interrupt and Data Flow
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