欢迎访问ic37.com |
会员登录 免费注册
发布采购

PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
 浏览型号PKM32AG-Q的Datasheet PDF文件第145页浏览型号PKM32AG-Q的Datasheet PDF文件第146页浏览型号PKM32AG-Q的Datasheet PDF文件第147页浏览型号PKM32AG-Q的Datasheet PDF文件第148页浏览型号PKM32AG-Q的Datasheet PDF文件第150页浏览型号PKM32AG-Q的Datasheet PDF文件第151页浏览型号PKM32AG-Q的Datasheet PDF文件第152页浏览型号PKM32AG-Q的Datasheet PDF文件第153页  
Ver 1.3  
PRELIMINARY  
EAGLE  
The Rendering X Start Point register configures the X coordinate of captured image displayed on screen.  
This register provides a 16-Pixel offset for image size in X coordination.  
3.16.8 Rendering Y Start Point Register (JICYSP)  
Address : 0xFFE0 500C  
Bit  
31:10  
9:1  
R/W  
R
R/W  
R
Description  
Default Value  
Reserved  
-
000h  
-
Y Display Start Coordinate [9:1] ( Vertical 2 Pixel Offset )  
Reserved  
0
The Rendering Y Start Point register configures the Y coordinate of captured image displayed on screen.  
This register provides a 2-line offset for image size in Y coordination.  
3.16.9 Rendering Base Start Address Register (JICBSA)  
Address : 0xFFE0 5010  
Bit  
31:20  
19:0  
R/W  
R/W  
R
Description  
Default Value  
Rendering Base Start Address  
Reserved  
000h  
-
This register indicates the base address for storing the decoded JPEG Images. When bit 4 of Control register is set as  
‘0’( Separate Address Use ), the Rendering Base Start Address should be specified. When bit 4 of Control Register is set as  
‘1’( Image Capture Engine Frame Buffer Use ), the value of this register has no affect.  
Both Local and Texture memory are supported. For Texture memory, bit 5 of Control Register should be set to ‘1’.  
The Rendering Base Start Address Register is set using 1 MByte unit.  
3.16.10 Rendering Status Register (JICSTAT)  
Address : 0xFFE0 5014  
Bit  
31  
30:28  
27:16  
15:12  
11:0  
R/W  
R
R
R
R
Description  
Default Value  
Interrupt Status  
Reserved  
X Image Size / 32  
Reserved  
0b  
-
000h  
-
R
Y Image Size / 32  
000h  
Interrupt Status bit indicates whether the operation of writing one frame image into Memory has completed or not. This bit  
is set to one whenever a frame image is written into memory. This bit will be cleared when bit 2 of JPEG Decoder Command  
Control register is asserted to ‘1’.  
The value in X / Y Image Size register is not the real image size value. The real image size value can be calculated by  
multiplying X / Y Size with 32. For example, when X Image Size Register has a value of 20, the Real X Image Size shall be  
640 (20 x 32).  
3.16.11 Rendering Y Offset Address Register (JICYOFFA)  
Address : 0xFFE0 5018  
Bit  
31:11  
10:5  
4:0  
R/W  
R
R/W  
R
Description  
Default Value  
Reserved  
Y Offset Address  
Reserved  
-
00h  
-
149  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
 复制成功!