Ver 1.3
PRELIMINARY
EAGLE
3.16.4 Operational Descriptions
AHB Interface Module, Engine Core, Engine DMAC & FIFO Controller and 512x32 Dual Port FIFO are the main modules
in JPEG Image Capturer.
1) AHB Interface Module :
The Bus Interface module for upper-layer AMBA. It includes Register Bank.
The Registers are used as signal controls for Engine operation and to report current module state of Master Device..
2) JPEG Image Capturer Core:
The Engine Core consists mainly of Main Control FSM, Pixel Gain Controller and Color Space Conversion.
Main Control FSM receives signals related to internal JPEG Decoder, such as X/Y Size, Data Enable, Format etc. and
controls the entire Engine operations. The Color Space Conversion module converts images from YCbCr format to RGB
format and Pixel Gain Controller controls the input gain of RGB Data.
Interrupt is generated when a frame image is completely written into memory.
3) Engine DMAC & FIFO Controller:
Engine DMA Controller executes the bus request based on Bus Request FIFO Level configuration as well as the FIFO
Level. To acquire authority control of bus, it communicates with Memory Controller to determine the Request Level.
FIFO Controller controls Dual Port Sync FIFO of size 512x32..
3.16.5 Engine Control Register (JICCON)
Address : 0xFFE0 5000
Bit
31 : 6
5
R/W
R
R/W
Description
Default Value
Reserved.
-
Texture Memory Use.
0: Local Memory Use
1: Texture Memory Use
0b
0b
4
R/W
CSC Image Capturer (CSC ICE) Address Area Use
0: Separate Address Use
1: CSC Image Capturer Frame Buffer Use
Reserved.
3
2
1
R
R/W
R/W
-
0b
User Y Offset Address Enable
Bit per Pixel
0: 16 bit RGB
1: 24 bit RGB
JPEG Image Capture(JPEG ICE) Enable
0: Disable
0b
0b
0
R/W
1: Enable
The bit 0 of Control register, Engine Enable bit, enables and disables the Engine.
All parameter should be set-up before setting Enable bit. Once enabled, there should be no parameter changes that might
affect the Engine operation.
Bit 1 of Control register indicates the number of bit per Pixel for converted RGB images stored in external memory by
JPEG Image Capturer (JPEG ICE). In 16 bit RGB mode, this bit can be used simultaneously with Graphic Rendering Engine
Image Processing function. Whereas in 24 bit RGB mode, this bit can not be used together with Graphic Rendering Engine
Image Processing function and bit 16 of CRT Control Register should be set to ‘1’ (24 bit RGB mode).
Bit 4 and 5 of Control register indicate Memory Map location for image storing.
Default value for bit 4 of Control register is ‘0’. When bit 4 is set to ‘1’, bit 2 and bit 5 of Control register is not
applicable,
When bit 4 is ‘0’, the Base Address (JICBSA) of memory map for image storing should be specified. In addition, the
Local / Texture memory is configured based on the value of bit 5 in Control register..
When bit 4 of Control register is ‘1’, Base Address (JICBSA) does not need to be specified as Render to Front Buffer /
Back Buffer set Bit at Graphic Rendering Engine and Frame Buffer area are automatically assigned through Memory Map to
CSC Image Capturer. Using both CSC Image Capturer block and JPEG Image Capturer when bit 4 is ‘1’, results in image
overlapping in the memory and it should be handled with caution.
147
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
