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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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EAGLE  
PRELIMINARY  
Ver 1.3  
5
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FIFO full Interrupt enable  
0 : disable  
1 : enable  
FIFO half full Interrupt enable  
0 : disable  
1 : enable  
FIFO empty Interrupt enable  
0 : disable  
1 : enable  
End command response Interrupt enable  
0 : disable  
0b  
0b  
0b  
0b  
0b  
0b  
4
3
2
1
0
1 : enable  
Write operation done Interrupt enable  
0 : disable  
1 : enable  
Read operation done Interrupt enable  
0 : disable  
1 : enable  
SDCSTAT[15:8] corresponds to the interrupt source while SDCIE register enables the interrupt. When an ISR (Interrupt  
Service Routine) is performed after an interrupt occurs, the bit located in SDCSTAT[15:8] which corresponds to that  
interrupt source should be cleared to ‘0’ by ISR. However, the interrupt sources corresponding to card insertion detection  
(SDCSTAT[15]) and card removal detection (SDCSTAT[14]) are not cleared. Hence their corresponding enabling register  
bits should be cleared by ISR.  
3.11.4.9 SDC Command Control Register (SDCCMDCON)  
SDCCMDCON is used by user to send a command. When user writes a command to SDCCMDCON, the corresponding  
command is transferred to SD Card.  
Address: FFE0 2420h  
Bit  
31 : 11  
10  
R/W  
R
R/W  
Description  
Default Value  
Reserved  
-
0b  
This bit indicates whether the command type requires a response or not.  
When configured as “no response”, response shall not be stored in the  
response buffer.  
0 : no response  
1 : wait for response  
9 : 8  
R/W  
These bits indicate the type of response. As response type is dependent on  
00b  
the command, proper response type selection with reference to the  
command type is needed.  
00 : short response (48bit)  
01 : short response with busy (R1b)  
10 : long response (136bit)  
7
6
R/W  
R/W  
R/W  
This bit indicates whether a command requires a data token or not. This  
bit should be set to ‘1’ for read or write command.  
0 : without data  
1 : with data  
This bit configures the I/O direction of data FIFO. For read command,  
this bit is set as ‘0’. For write command, this bit is set as ‘1’.  
0 : read data  
1 : write data  
0b  
0b  
5 : 0  
These bits indicate the number of command. Since the meaning of  
00h  
command number in MMC is different from SD Card, refer to their  
respective specification for further details.  
00h = CMD0  
01h = CMD1  
...  
3Fh = CMD63  
Beijing Peak Microtech Co.Ltd.  
CONFIDENTIAL  
118  
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