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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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Ver 1.3  
PRELIMINARY  
EAGLE  
3.11.4 Register Description  
3.11.4.1 SDC Control Register (SDCCON)  
Address : FFE0 2400h  
Bit  
31 : 6  
5
R/W  
R
R/W  
Description  
Default Value  
Reserved  
MMC/SD HC Enable  
-
0b  
Enable bit for SD Controller. If this bit is set as “Disable”, the controller  
will return to initial state and all buffers are cleared.  
0 : Disable (Controller is initialized)  
1 : Enable  
4 : 3  
R/W  
R/W  
Memory access type  
This bit decides the byte size for reading or writing data to system  
memory.  
00 : Bytes access, read or write data in 1 byte unit.  
01 : short access, read or write data in 2 byte unit.  
10 : long access, read or write data in 4 byte unit.  
11 : not used.  
00b  
0b  
2
DMA mode selection  
This bit enables fast data transmission mode using GDMA which is  
available in Eagle platform.  
0 : Normal mode (data transfer by CPU)  
1 : DMA mode (data transfer by GDMA)  
Bus width Selection  
0 : 1bit data bus  
1 : 4bit data bus  
1
0
R/W  
R/W  
0b  
0b  
MMC/SD clock enable  
0 : Disable  
1 : Enable  
3.11.4.2 SDC Status Register (SDCSTAT)  
Address: FFE0 2404h  
Bit  
31 : 16  
15  
R/W  
R
R
Description  
Default Value  
Reserved  
Card_Insertion  
-
0b  
This bit indicates the insertion of SD Card through data line[3]. Pull-  
down resistor should be added to data line[3].  
0 : No card insertion detection  
1 : Card insertion detected  
14  
R
Card_Removal  
0b  
This bit indicates the removal of SD Card through data line[3].  
0 : No card removal detected  
1 : Card removal detected  
13  
12  
11  
10  
R
R
FIFO full  
0b  
0b  
1b  
0b  
This bit indicates that the 64-byte data FIFO is in full  
FIFO half full  
This bit indicates that the 64-byte data FIFO is half-full.  
R
FIFO empty  
This bit indicates that the 64-byte data FIFO is empty.  
Command & response transaction done  
This bit indicates the completion of a transaction which includes the  
reception of response from SD Card as accordance to the command sent  
by Controller. This bit is also set to ‘1’ when a transaction completes with  
an error condition, such as response is not received.  
0 : Command and response transaction is in progress  
1 : Command and response transaction is done  
Write operation done  
R/C  
9
R/C  
0b  
115  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
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