Ver 1.3
PRELIMINARY
EAGLE
3.12.3 Channel Register Map
3.12.3.1 Sound Data Channel n Control Register (SNDCONn)
This register sets the data operation method for each channel.
Address: FFE0 3000h / FFE0 3020h / FFE0 3040h / FFE0 3060h / FFE0 3080h / FFE0 30A0h / FFE0 30C0h
/ FFE0 30E0h
Bit
31 : 30
29
R/W
R
R/W
Description
Default Value
Reserved
-
0b
Endian (For 32-bit)
0 : Little Endian
1 : Big Endian
Endian (For 16-bit)
0 : Little Endian
1 : Big Endian
Pan pot
Left / Right Balance
16 steps
Total Level
Volume
256 steps
Channel Interrupt
0 : Disable
1 : Enable
28
R/W
R/W
R/W
R/W
R/W
0b
0h
27 : 24
23 : 16
15
FFh
0b
14 : 13
Quantization mode
00b
00 : Ignore mode setting and set to same state as Channel On = ‘Off’
01 : 4-bit ADPCM mode
10 : 8-bit linear PCM mode
11 : 16-bit linear PCM mode
Loop
0 : Disable
1 : Enable
12
11
R/W
W
0b
-
Channel Off
10 : 8
7 : 0
R
R/W
Reserved
Playback pitch
-
FFh
256 steps (0.172 to 44.1kHz)
The Endian bits provide a 16-bit or 32-bit Byte-swap capability .
The Pan pot bit contains the value of 16 steps with a center value of '8h' and allows the control of Left / Right
Balance. The total level of channel volume is 256 steps and it is controllable within the 256-step range.
When interrupt is enabled, interrupts shall be generated for the Half / End Addresses of each channel.
The Quantization mode bit sets the sound data format. When set as ‘0’, the channel shall remain in OFF state.
The Loop bit is used for sound data repetition within the range of Start Address up to the value configured in
SNDSIZn register. If Loop is disabled, the corresponding Channel will stay Off starting from the End Address.
Otherwise if enabled, Loop Play runs continuously until the Channel is configured to Off.
The Channel Off bit allows user to disable sound Mixer’s channel by force without waiting for end address.
The Playback pitch sets the sampling rate of sound data, in 256 steps from 0.172 KHz to 44.1 KHz
3.12.3.2 Sound Data Channel n Start Address Set Register (SNDADRn)
This register identifies the external memory start address for each channel access.
Address: FFE0 3004h / FFE0 3024h / FFE0 3044h / FFE0 3064h / FFE0 3084h / FFE0 30A4h / FFE0 30C4h
/ FFE0 30E4h
Bit
R/W
Description
Default Value
31 : 0
R/W
Start Address
0h
121
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
