EAGLE
PRELIMINARY
Ver 1.3
3.12.3.3 Sound Data Channel n Size Set Register (SNDSIZn)
This register identifies the external memory sound buffer size for each channel access.
Address: FFE0 3008h / FFE0 3028h / FFE0 3048h / FFE0 3068h / FFE0 3088h / FFE0 30A8h / FFE0 30C8h
/ FFE0 30E8h
Bit
31 : 22
21 : 0
R/W
R
R/W
Description
Default Value
Reserved
Sound data Size
-
0h
The sound data size is determined starting from the Start Address of Sound Buffer.
3.12.3.4 Sound Data Channel On / Status Register (SNDCHON)
This register controls the channel On / Off state.
Address: FFE0 3010h
Bit
31 : 24
23 : 16
R/W
R
R
Description
Default Value
Reserved
Channel busy
Ch 7 ~ Ch 0
-
0h
15 : 8
7 : 0
R/W
Channel pause
Ch 7 ~ Ch 0
Channel On / Status
Ch 7 ~ Ch 0
0h
0h
R /W
The Channel busy bit indicates the busy status of each channel. When channel operation is completed and FIFO
becomes empty, this bit is cleared to ‘0’.
Channel pause bit sets the pause of each channel.
When all configurations are set properly, Channel On / Status bit is used to turn the corresponding Channel<n> 'On'.
This bit shall remain at ‘0’ if the Quantization mode in SNDCONn’ Register is set to '00'. If Loop is disabled, the
corresponding Channel will be automatically changed to ‘Off” when End Address is encountered.
3.12.3.5 Sound Data Channel Interrupt Status Register (SNDIRQSTAT)
This register indicates the sound buffer Half / End address for each channel access.
Address: FFE0 3014h
Bit
31 : 16
15 : 8
R/W
R
R
Description
Default Value
Reserved
Half Flag of Channel n
Ch 7 ~ Ch 0
-
0h
7 : 0
R
End Flag of Channel n
Ch 7 ~ Ch 0
0h
Half / End Flag Channel<n> bits are asserted when interrupts are generated at Half / End Addresses of Sound Buffer
if interrupt is enabled in ‘SNDCONn’ register.
When an interrupt occurs, the corresponding interrupt flag bit will be set to ‘1’, and cleared to ‘0’ when this bit is
read or interrupt is disabled.
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CONFIDENTIAL
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