DRL7
BCD to 7 segment decoder/driver
SRB8
SRB8A
SRC8
SRD4
SRE4
2 bit PISO shift register with clear
2 bit PISO shift register without clear
8 bit PISO shift register with clear
8 bit SIPO shift register with clear
4 bit PIPO shift register with JKbar
input
ENCODERS
ENA8T3
ENB10T4
8 line to 3 line priority encoder
10 line to 4 line priority encode
SRF8
SRG4
8 bit shift and store register with
tristate outputs
4 bit bidirectional universal shift
FLIP-FLOP
register
FFA8
FFB6
FFC4
8 bit bistable latches
SRJ4
SRK5
4 bit parallel access shift register
5 bit shift register
6 bit D-type flip-flop with clear
4 bit D-type flip-flop with clear &
complimentary outputs
PROCESS MONITOR
FFD8
Octal D-type flip-flop with clear
PERF
Performance monitor
ALU/FUNCTIONAL GENERATOR
BIST *
FGA5
4 bit ALU/function generator
RGBIT
Test register (one bit)
Test register (one monitor bit)
Diagnostic control unit
Test register controller
Test register hold circuitry
ADDERS
MCA4
RGTBIT
RGDIAG
RGCTL
RGHOLD
4 bit magnitude comparators
MULTIPLIERS
MLA10
* (early built in self test cells) see CLA7BIST Library
Decade rate multiplier
MLB4X4
4 by 4 binary multiplier with tristate
outputs
CLA70000 PARACELL LIBRARY
MLW7
7 bit Wallace trees with tristate
outputs
MEMORY CELLS
RBRAM
ROROM
RAM MAX 16384 bits per block
WORDS 2:128, bits 1:128 (min:max)
ROM MAX 65536 bits per block
WORDS 2:2048, bits 2:64 (min:max)
MULTIPLEXERS
MXA8T1
8 line to 1 line data selector /
multiplexer
MXB4T1
Dual 4 line to 1 line data selector /
multiplexers
MXB4T1A
Dual 4 line to 1 line data selector /
multiplexer with inverted tristate
outputs
MXC2T1
MXC2T1A
MXD4T1
MXE4T1
MXF2T1
Quad 2 to 1 data selector / multiplexers
Quad 2 to 1 selector (inverted outputs)
4 to 1 multiplexor with strobe
4 to 1 multiplexor with strobe
2 to 1 multiplexeor with storage
PARITY GENERATOR
PGA9
9 bit odd/even parity
generator/checker
SHIFT REGISTERS
SRA2
SRA4
SRA8
SRA8A
SRB2
SRB4
2 bit POS shift register with clear
4 bit POS shift register with clear
8 bit SIPO shift register with clear
8 bit SIPO shift register without clear
2 bit PISO shift register with clear
4 bit PISO shift register with clear
ETC [ ETC ]
