MUXI4TO1 4 to 1 inverting multiplexer
MUXI8TO 1 8 to 1 inverting multiplexer
IBGATE
IBCLKB
IBDF
IBDFA
IBSK1
IBSK2
IBSK3
IBTRID
IBTRID1
NAND2/NOR2 gates
Large clock driver
Master-slave D type flip flop
Master-slave D type flip flop
Driver with slewed outputs
Driver with slewed outputs
Driver with slewed outputs
Tri-state driver
Tri-state driver with slewed outputs +
2 inverters
Tri-state driver with slewed outputs +
2 inverters
CLKA
Basic clock driver
2CLKA
CLKAP
CLKAM
CLKB
CLKBP
CLKE1
CLKE2
CLKE3
Dual basic clock driver
Basic clock driver + inverter
Basic clock driver + inverter
Large clock driver + inverter
Large clock driver + inverter
Clock driver with enable
Clock driver with enable
Clock driver with enable
IBTRID2
IBTRID3
IB2BD
Tri-state driver with slewed outputs +
2 inverters
Dual high powered inverters
TM
2TM
BDR
Buffered transmission gate
Transmission gate for 2 to 1 multiplexing
Internal bus driver
DRV3
DRV6
Clock driver
Clock driver
DL
DL2
Data latch
Data latch
DLRS
DLARS
DF
DFRS
MDF
MDFRS
Data latch with set and reset
Data latch with set and reset
Master-slave D type flip flop
Master-slave D type flip flop with set & reset
Multiplexed master-slave D type flip flop
Multiplexed master-slave D type flip flop
with set & reset
Multiplexed m/s D type flip flop
Multiplexed m/s D type flip flop
with set & reset
PAD INPUT CELLS
IPNR
Input cell with no pull up or down resistors
IPR1P
IPR1M
IPR2P
IPR2M
IPR3P
IPR3M
IPR4P
IPR4M
Input cell with 1KOhm pull up resistor
Input cell with 1KOhm pull down resistor
Input cell with 2KOhm pull up resistor
Input cell with 2KOhm pull down resistor
Input cell with 4KOhm pull up resistor
Input cell with 4KOhm pull down resistor
Input cell with 75KOhm pull up resistor
Input cell with 75kOhm pull down resistor
M3DF
M3DF
JK
J-K flip-flop
JKRS
JBARK
JBARKRS
J-K flip-flop with set & reset
JBAR-K flip-flop
JBAR-K flip-flop with set & reset
OSCILLATOR CELLS (crystal)
to be defined
BDL
Buffered data latch
PAD OUTPUT CELLS
BDLRS
JBARKRS
BDF
Buffered data latch with set & reset
Buffered data latch with set & reset
Buffered master-slave D type flip-flop
Buffered master-slave D type flip-flop
with set & reset
Buffered mux. master-slave D type flip-flop
Buffered mux. m/s D type with set & reset
Buffered J-K flip-flop
OP1
OP2
OP3
OP6
OP12
Smallest drive output cell
Small drive output cell
Standard drive output cell
Medium drive output cell
Large drive output cell
BDFRS
BMDF
BMDFRS
BJBARK
OP5B
OP11B
Standard drive non-inverting output cell
Large drive non-inverting output cell
BJBARKRS Buffered J-K flip-flop with set & reset
TRID
Tristate driver
OPT1
OPT2
OPT3
OPT6
OPT12
Smallest drive tri-state output cell
Small drive tri-state output cell
Standard drive tri-state output cell
Medium drive tri-state output cell
Large drive tri-state output cell
GND
VDD
Ground Cell
VDD Cell
INTERMEDIATE BUFFER CELLS
OP4B
Standard drive non-inverting tri-state output
cell
Large drive non-inverting tri-state output cell
IBCCMOS1 CMOS input buffer + large 2 input NAND gate
IBCCMOS2 CMOS input buffer + data latch
OP10B
IBTTL1
IBBTL2
IBST1
TTL input buffer + large 2 input NAND gate
TTL input buffer + data latch
Input Schmitt buffer with CMOS switching
levels
OPOD1
OPOD2
OPOD3
OPOD6
OPOD12
Smallest drive open-drain output cell
Small drive open-drain output cell
Standard drive open-drain output cell
Medium drive open-drain output cell
Large drive open-drain output cell
IBST2
Input Schmitt buffer with 2V switching levels
ETC [ ETC ]
