CELL LIBRARY
MANUFACTURING FACILITY
■ Computer aided manufacturing
■ Comprehensive range of cells
■ Specialized DSP and BIST sub-libraries
■ Compatible with Megacell and CLA60000
■ Digital testers with large pinout capacity
■ Vibration free for reliable manufacture
A very comprehensive cell library is available for the
CLA70000 series. It contains sub libraries which may be used
in specific applications areas such as Digital Signal
Processing (DSP) and Built In Self Test (BIST).
More details on these specialized libraries can be found in
applications notes or the design manual.
The CLA70000 product is manufactured near Plymouth,
England in the latest purpose built facility for sub-micron
process geometries. The factory uses the latest automated
equipment for 6 inch wafers and Computer Aided
Manufacturing techniques to ensure production efficiency.
Wafer fabrication is carried out in Class 10, or better, clean
room conditions in a vibration free environment to assure the
lowest possible defect level. In addition to the world class
wafer facility there are excellent probe and final test areas
equipped with the latest analog and digital testers capable of
handling complex test vectors and large pinouts. This large
investment shows GEC Plessey Semiconductors
commitment to all the market areas needing state-of-the-art
CMOS ASICS.
The 1.4 micron (drawn) CMOS array (CLA60000) cell
library may be converted to the equivalent cells on the
CLA70000 to allow system upgrades. Equivalent cells are
also available for the corresponding MVA70000 Megacell to
enable an easy transition to a standard cell product to
minimize silicon area or to add analog functions.
A2O31
O2A31
A3O21
O3A21
A4O21
O4A21
A2041
O2A41
3A2O31
3O2A31
O2A2O21
2 input AND to 3 input NOR gate
2 input OR to 3 NAND gate
CELL LIBRARY
3 input AND to 2 input NOR gate
3 input OR to 2 input NAND gate
4-input ANDs to 2 input NOR gate
4-input ORs to 2 input NAND gate
2-input AND to 4 input NOR gate
2-input ORs to 4 input NAND gate
3 2-input ANDs to 3 input NOR gate
3 2-input ORs to 3 input NAND gate
2 input OR to 2 input AND to 2 input
NOR gate
LOGIC ARRAY CELLS
BUF
ST1
DELAY
Buffer driver
Schmitt trigger
Delay cell
2INV
INV2
INV4
INV8
Dual driver
Inverter, dual drive
Inverter, quad drive
Inverter, octal drive
A2O2A21
2 input AND to 2 input OR to 2 input
NAND gate
NAND2
ND3
2 input NAND gate
3 input NAND gate
EXOR
Exclusive OR gate + NAND gate + inverter
Exclusive NOR gate + NOR gate + inverter
2 input exclusive OR gate
2 input exclusive NOR gate
Exclusive OR gate + inverter
Exclusive NOR gate + inverter
3 input exclusive OR gate
3 input exclusive NOR gate
NAND3
2NAND3
NAND4
NAND5
NAND6
NAND8
3 input NAND gate + inverter
Dual 3 input NAND gate
4 input NAND gate
5 input NAND gate
6 input NAND gate
EXNOR
EXOR2
EXNOR2
EX2
EXN2
8 input NAND gate
EXOR3
EXNOR3
EXPRIM
NOR2
NR3
2 input NOR gate
3 input NOR gate
2 input exclusive OR gate primitive
NOR3
2NOR3
NOR4
NOR5
NOR6
NOR8
3 input NOR gate + inverter
Dual 3 input NOR gate
4 input NOR gate
5 input NOR gate
6 input NOR gate
HADD
SUM
Half adder + inverter
Sum block
Sum block
Carry block + NOR gate
Carry block + inverter
Full adder + NOR gate
Full adder 1
SUM2
CARRY
CARRY2
FADD
BMF1
BMF2
8 input NOR gate
A2O21
O2A21
2A2O21
2O2A21
2ANOR
2 input AND to 2 input NOR gate + inverter
Full adder 2
2 input OR to 2 input NAND gate + inverter
Dual 2 input AND to 2 input NOR gate
Dual 2 input OR to 2 input NAND gate
2 input ANDs to 2 input NOR gate
MUX2TO1
MUX4TO1
MUX8TO1
2 to 1 multiplexer
4 to 1 multiplexer
8 to 1 multiplexer
2ONAND
2 input ORs to 2 input NAND gate
MUXI2TO1 2 to 1 inverting multiplexer
ETC [ ETC ]
