ADM7008
Electrical Specification
5.4 SMII Clock Timing
5.4.1 REFCLK Input Timing (When REFCLK_SEL is set to 1) -
Also apply to TX_CLK
t_IN125_PER
t_IN125_HI
t_IN125_LO
VIH_SMII
VIL_SMII
REFCLK
t_IN125_RISE
t_IN125_FALL
Figure 5-6 REFCLK Input Timing
Symbol
Description
MIN
8.0 -
TYP
MAX UNIT
t_IN125_PER
REFCLK/TXCLK Clock Period
8.0
8.0 + ns
50ppm
50pp
m
t_IN125_HI
t_IN125_LO
REFCLK/TXCLK Clock High
REFCLK/TXCLK Clock Low
2.8
2.8
4.0
4.0
ns
ns
t_IN125_RISE REFCLK/TXCLK Clock Rise Time , VIL (max)
2
2
ns
to VIH (min)
t_IN125_FALL REFCLK/TXCLK Clock Fall Time , VIH (min)
to VIL (max)
ns
Table 5-9 REFCLK Input Timing
ADMtek Inc.
5-7
ETC [ ETC ]
