ADM7008
Electrical Specification
5.3.4 RMII Receive Timing
REFCLK
t_RR_ML2CSL
NON_IDLE
(Internal)
t_RR_MH2CSH
CRSDV
t_RR_CSL2DAT
t_RR_DDLY
t_RR_CSH2DAT
PREAM
PREAM
RXD0
RXD1
RXD2
RXD4
RXD5
RXD6
RXDN
00
RXD
Figure 5-5 RMII Receive Timing
Symbol
Description
MIN
TYP
MAX UNIT
265 ns
t_RR_MH2CSH1 Signal Detected on Medium to CRSDV High
00
t_RR_MH2CSH1 Signal Detected on Medium to CRSDV High
0
1000 ns
t_RR_ML2CSL10 IDLE Detected on Medium to CRSDV low
0
260
ns
t_RR_ML2CSL10 IDLE Detected on Medium to CRSDV low
570
160
ns
ns
t_RR_CSH2DAT CRSDV High to Receive Data on RXD
t1_00RR_CSH2DAT CRSDV High to Receive Data on RXD
t1_0 RR_CSL2DAT CRSDV Toggle to End of Data Receiving
t1_00RR_CSL2DAT CRSDV Toggle to End of Data Receiving
1600 ns
160
ns
ns
1600
t1_0 RR_DDLY
REFCLK Rising to RXD/CRSDV Delay Time
5
ns
Table 5-8 RMII Receive Timing
ADMtek Inc.
5-6
ETC [ ETC ]
