ADM7008
Electrical Specification
5.4.2 REFCLK Output Timing (When REFCLK_SEL is set to 1)
Also apply to RXCLK in SS_SMII Mode
t_OUT125_PER
t_OUT125_PER
t_OUT125_HI
t_OUT125_HI
t_OUT125_LO
t_OUT125_LO
VIH_SMII
VIH_SMII
VIL_SMII
VIL_SMII
REFCLK
REFCLK
t_OUT125_RISE
t_OUT125_RISE
t_OUT125_FALL
t_OUT125_FALL
Figure 5-7 SMII/SS_SMII REFCLK Output Timing
Symbol
Description
MIN
8.0 -
TYP
MAX UNIT
t_OUT125_PER REFCLK Clock Period
8.0
8.0 + ns
50ppm
50pp
m
t_OUT125_HI
REFCLK Clock High
2.4
2.4
4.0
4.0
ns
ns
ns
t_OUT125_LO REFCLK Clock Low
t_OUT125_RISE REFCLK Clock Rise Time , VIL (max) to VIH
(min)
26
2
t_OUT125_FAL REFCLK Clock Fall Time , VIH (min) to VIL
2
ns
ns
L
(max)
t_OUT125_JIT REFCLK Clock Jittering (p-p)
0.15
Table 5-10 SMII/SS_SMII REFCLK Output Timing
ADMtek Inc.
5-8
ETC [ ETC ]
