ADM7008
Electrical Specification
5.4.4 SMII/SS_SMII Receive Timing
TXCLK (SMII)
RXCLK(SS_SMII)
NON_IDLE
(Internal)
t_SR_MH2DVH
t_SR_ML2CSL
SYNC (SMII)
RX_SYNC (SS_SMII)
t_SR_DDLY
t_SR_MH2CSH
CRS
= 1
RXDV
= 0
CRS
= 1
RXDV
= 1
CRS
= 0
RXDV
= 0
RXD5
VALID
RXD6
FCE
RXD7
RXD7
RXD
Figure 5-9 SMII/SS_SMII Receive Timing
Symbol
Description
MIN
TYP
MAX UNIT
t_SR_MH2CSH10 Signal Detected on Medium to CRS High
430
680
420
ns
ns
ns
(100M)
0
t_SR_MH2CSH10 Signal Detected on Medium to CRS High
(10M)
t_SR_ML2CSL10 IDLE Detected on Medium to CRS low (100M)
t0_SR_ML2CSL10 IDLE Detected on Medium to CRS low (10M)
t_SR_MH2DVH1 Signal Detected on Medium to Receive Data
240
470
ns
ns
Valid (100M)
00
t_SR_MH2DVH1 Signal Detected on Medium to Receive Data
0
3840 ns
Valid (10M)
t_SR_DDLYSMII TXCLK Rising to SYNC/RXD Delay Time
(SMII)
5
5
ns
ns
t_SR_DDLYSS_S RXCLK Rising to RX_SYNC/RXD Delay
Time (SS_SMII)
MII
Table 5-12 SMII/SS_SMII Receive Timing
ADMtek Inc.
5-10
ETC [ ETC ]
