ADM7008
Electrical Specification
5.3 RMII Timing
5.3.1 REFCLK Input Timing (When REFCLK_SEL is set to 1)
t_IN50_PER
t_IN50_HI
t_IN50_LO
VIH_RMII
VIL_RMII
t_IN50_RISE
t_IN50_FALL
Figure 5-2 REFCLK Input Timing
Symbol
Description
MIN
TYP
MAX UNIT
t_IN50_PER
REFCLK Clock Period
40.0 - 40.0
50ppm
40.0 + ns
50pp
m
t_IN50_HI
t_IN50_LO
t_IN50_RISE
REFCLK Clock High
14
14
20.0
20.0
ns
REFCLK Clock Low
ns
REFCLK Clock Rise Time , VIL (max) to VIH
2
2
ns
(min)
t_IN50_FALL
REFCLK Clock Fall Time , VIH (min) to VIL
(max)
ns
Table 5-5 REFCLK Input Timing
ADMtek Inc.
5-3