ADM7008
Electrical Specification
5.3.2 REFCLK Output Timing (When REFCLK_SEL is set to 0)
t_OUT50_PER
t_OUT50_HI t_OUT50_LO
VIH_RMII
VIL_RMII
t_OUT50_RISE
t_OUT50_FALL
Figure 5-3 REFCLK Output Timing
Symbol
Description
MIN
TYP
MAX UNIT
40.0 + ns
50pp
t_OUT50_PER REFCLK Clock Period
40.0 - 40.0
50ppm
m
t_OUT50_HI
t_OUT50_LO
REFCLK Clock High
REFCLK Clock Low
14
14
20.0
20.0
26
26
2
ns
ns
ns
t_OUT50_RISE REFCLK Clock Rise Time , VIL (max) to VIH
(min)
t_OUT50_FALL REFCLK Clock Fall Time , VIH (min) to VIL
(max)
t_OUT50_JIT
2
ns
ns
REFCLK Clock Jittering (p-p)
0.15
Table 5-6 REFCLK Output Timing
ADMtek Inc.
5-4
ETC [ ETC ]
