ADM7008
Function Description
3.3.4 RMII Mode (RSMODE1 = 1)
LED_CLK
SPEE
D0
SPEE
D1
SPEE
D2
SPEE
D3
SPEE
D4
SPEE
D5
SPEE
D6
SPEE
D7
DUPCOL
0
DUPCOL
1
DUPCOL
2
DUPCOL
3
DUPCOL
4
DUPCOL
5
DUPCOL
6
DUPCOL
7
LNKACT
0
LNKACT
1
LNKACT
2
LNKACT
3
LNKACT
4
LNKACT
5
LNKACT
6
LNKACT
DUPCOL
0
LED_DATA
7
Figure 3-21 Stream LED under RMII Mode
3.3.5 SMII/SS_SMII Mode (RSMODE1 = 0)
LED_CLK
SPEE
D0
SPEE
D1
SPEE
D2
SPEE
D3
SPEE
D4
SPEE
D5
SPEE
D6
SPEE
D7
DUPCOL
0
DUPCOL
1
DUPCOL
2
DUPCOL
3
DUPCOL
4
DUPCOL
5
DUPCOL
6
DUPCOL
7
LNKACT
0
LNKACT
1
LNKACT
2
LNKACT
3
LNKACT
4
LNKACT
5
LNKACT
6
LNKACT
7
DUPCOL
0
LED_DATA
Figure 3-22 Stream LED under SMII/SS_SMII Mode
The high duration for LED_CLK is 40ns and the low duration is 600ns to form 640ns
period clock. ADM7008 will burst 24 bit status in one time in order to display internal
LINK/Activity, Duplex/Collision and Speed status according to different mode. When a
burst is completed, LED_CLK will keep low for 40 ms and system can use it to
distinguish between two bursts.
3.4 Management Register Access
The SMI consists of two pins, management data clock (MDC) and management data
input/output (MDIO). The ADM7008 is designed to support an MDC frequency
specified in the IEEE specification of up to 2.5 MHz. The MDIO line is bi-directional
and may be shared by up to 32 devices.
The MDIO pin requires a 1.5 KΩ pull-up which, during idle and turnaround periods, will
pull MDIO to a logic one state. Each MII management data frame is 64 bits long. The
first 32 bits are preamble consisting of 32 contiguous logic one bits on MDIO and 32
corresponding cycles on MDC. Following preamble is the start-of-frame field indicated
by a <01> pattern. The next field signals the operation code (OP) : <10> indicates read
from MII management register operation, and <01> indicates write to MII management
register operation. The next two fields are PHY device address and MII management
register address. Both of them are 5 bits wide and the most significant bit is transferred
first.
ADMtek Inc.
3-24
ETC [ ETC ]
