ADM7008
Function Description
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Power Management
Clock Generator
Voltage Regulator
Each 10/100M PHY block contains:
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10M PHY block
100M PHY block
Auto-negotiation
Cable Broken Detector
Other Digital Control Blocks
3.1 10/100M PHY Block
The 100Base-X section of the device implements he following functional blocks :
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100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
Twisted-pair PMD (TP-PMD) transceiver
The 100Base-X and 10Base-T sections share the following functional blocks :
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Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
The interfaces used for communication between PHY block and switch core is MII
interface.
3.1.1 100Base-X Module
ADM7008 implements 100Base-X compliant PCS and PMA and 100Base-TX compliant
TP-PMD as illustrated in Figure 4. Bypass options for each of the major functional
blocks within the 100Base-X PCS provides flexibility for various applications. 100
Mbps PHY loop back is included for diagnostic purpose.
3.1.2 100Base-TX Receiver
For 100Base-TX operation, the on-chip twisted pair receiver that consists of a differential
line receiver, an adaptive equalizer and a base-line wander compensation circuits detects
the incoming signal.
ADM7008 uses an adaptive equalizer that changes filter frequency response in
accordance with cable length. The cable length is estimated based on the incoming signal
strength. The equalizer tunes itself automatically for any cable length to compensate for
the amplitude and phase distortions incurred from the cable.
The 100Base-X receiver consists of functional blocks required to recover and condition
the 125 Mbps receive data stream. The ADM7008 implements the 100Base-X receiving
state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125
Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a
ADMtek Inc.
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ETC [ ETC ]
