ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU)
6.6 RESET/STOP MANAGER
The Reset/Stop Manager resets the MCU when
one of the three following events occurs:
TRES or the WDGRES bits respectively; a hard-
ware initiated reset will leave both these bits reset.
– A Hardware reset, initiated by a low level on the
RESET pin.
The hardware reset overrides all other conditions
and forces the ST9 to the reset state. During Re-
set, the internal registers are set to their reset val-
ues, where these are defined, and the I/O pins are
set to the Bidirectional Weak Pull-up mode.
– A Software reset, initiated by a HALT instruction
(when enabled).
– A Watchdog end of count condition.
Reset is asynchronous: as soon as the RESET pin
is driven low, a Reset cycle is initiated.
The event which caused the last Reset is flagged
in the CLK_FLAG register, by setting the SOF-
Figure 41. Oscillator Start-up Sequence and Reset Timing
V
V
MAX
MIN
DD
DD
OSCIN
OSCOUT
12ms (5V), 24ms (3V)
INTCLK
RESET
PIN
VR02085A
78/199
9
ETC [ ETC ]
