ST72104G, ST72215G, ST72216G, ST72254G
MISCELLANEOUS REGISTERS (Cont’d)
11.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Reset Value: 0000 0000 (00h)
7
0
f
in SLOW mode
CP1
CP0
CPU
IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS
f
f
/ 4
/ 8
0
1
0
1
0
0
1
1
OSC
OSC
f
f
/ 16
/ 32
OSC
OSC
Bit 7:6 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1 (interrupt masked).
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = fOSC / 2
ei1: Port B (C optional)
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
External Interrupt Sensitivity
IS11 IS10
See low power consumption mode and MCC
chapters for more details.
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PC2 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
on I/O
CPU
port)
Bit 4:3 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1 (interrupt masked).
ei0: Port A (C optional)
External Interrupt Sensitivity
IS01 IS00
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
37/140
ETC [ ETC ]
