ST6200C/ST6201C/ST6203C
8-BIT TIMER (Cont’d)
9.2.3 Counter/Prescaler Description
caler and the counter run at the rate of the select-
ed clock source.
Prescaler
Counter and Prescaler Initialization
The prescaler input can be the internal frequency
f
divided by 12 or an external clock applied to
After RESET, the counter and the prescaler are in-
itialized to 0FFh and 7Fh respectively.
INT
the TIMER pin. The prescaler decrements on the
rising edge, depending on the division factor pro-
grammed by the PS[2:0] bits in the TSCR register.
The 7-bit prescaler can be initialized to 7Fh by
clearing the PSI bit. Direct write access to the
prescaler is also possible when PSI =1. Then, any
value between 0 and 7Fh can be loaded into it.
The state of the 7-bit prescaler can be read in the
PSCR register.
When the prescaler reaches 0, it is automatically
reloaded with 7Fh.
The 8-bit counter can be initialized separately by
writing to the TCR register.
9.2.3.1 8-bit Counting and Interrupt Capability
on Counter Underflow
Counter
The free running 8-bit downcounter is fed by the
output of the programmable prescaler, and is dec-
remented on every rising edge of the f
clock signal coming from the prescaler.
Whatever the division factor defined for the pres-
caler, the Timer Counter works as an 8-bit down-
counter. The input clock frequency is user selecta-
ble using the PS[2:0] bits.
COUNTER
It is possible to read or write the contents of the
counter on the fly, by reading or writing the timer
counter register (TCR).
When the downcounter decrements to zero, the
TMZ (Timer Zero) bit in the TSCR is set. If the ETI
(Enable Timer Interrupt) bit in the TSCR is also
set, an interrupt request is generated.
When the downcounter reaches 0, it is automati-
cally reloaded with the value 0FFh.
The Timer interrupt can be used to exit the MCU
from WAIT or STOP mode.
Counter clock and prescaler
The TCR can be written at any time by software to
define a time period ending with an underflow
event, and therefore manage delay or timer func-
tions.
The counter clock frequency is given by:
PS[2:0]
f
= f
/ 2
COUNTER
PRESCALER
where f
can be:
PRESCALER
– f /12
INT
TMZ is set when the downcounter reaches zero;
however, it may also be set by writing 00h in the
TCR registeror bysetting bit 7ofthe TSCR register.
– f
(input on TIMER pin)
EXT
– f /12 gated by TIMER pin
INT
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine.
The timer input clock feeds the 7-bit programma-
ble prescaler. The prescaler output can be pro-
grammed by selecting one of the 8 available pres-
caler taps using the PS[2:0] bits in the Status/Con-
trol Register (TSCR). Thus the division factor of
Note: A write to the TCR register will predominate
over the 8-bit counter decrement to 00h function,
i.e. if a write and a TCR register decrement to 00h
occur simultaneously, the write will take prece-
dence, and the TMZ bit is not set until the 8-bit
counter underflows again.
n
the prescalercan be set to 2 (where n equals 0, to
7). See Figure 27.
The clock input is enabled by the PSI (Prescaler
Initialize) bit in the TSCR register. When PSI is re-
set, the counter is frozen and the prescaler is load-
ed with the value 7Fh. When PSI is set, the pres-
46/104
1
ETC [ ETC ]
