ST6200C/ST6201C/ST6203C
5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources:
Table 6 illustrates various possible oscillator con-
figurations using an external crystal or ceramic
resonator, an external clock input, an external re-
NET
the LFAO.
– external clock signal
sistor (R
), or the lowest cost solution using only
– external AT-cut parallel-resonant crystal
– external ceramic resonator
For more details on configuring the clock options,
refer to the Option Bytes section of this document.
– external RC network (R
).
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The internal MCU clock frequency (f ) is divided
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
INT
by 12 to drive the Timer, the Watchdog timer and
the A/D converter (if available), and by 13 to drive
the CPU core, as shown in Figure 9.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in the event of main oscil-
lator failure. It also automatically limits the internal
With an 8 MHz oscillator, the fastest CPU cycle is
therefore 1.625µs.
A CPU cycle is the smallest unit of time needed to
execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.
clock frequency (f ) as a function of V , in order
INT
DD
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
Figure 9. Clock Circuit Block Diagram
OSCILLATOR SAFEGUARD (OSG)
CORE
: 13
f
OSG
OSC
filtering
8-BIT TIMER
WATCHDOG
0
1
f
MAIN
OSCILLATOR
INT
: 12
*
ADC
LFAO
OSCOFF BIT
(ADCR REGISTER)
*
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)
* Depending on device. See device summary on page 1.
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ETC [ ETC ]
