PIC16F87X
9.1.2
SLAVE MODE
While in sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from sleep.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
Note: When the SPI module is in Slave Mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
While in slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note: If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
1999 Microchip Technology Inc.
DS30292B-page 69
ETC [ ETC ]
