IP1001 LF
Data Sheet
4.15 PHY Specific Control Register2 (Reg20)
HW
Reset
SW
Reset
Bit
Name
Description
Type
20[1:0]
20.2
SR_V/ SR_FAST Sew rate control parameters
RW
RW
11
NA
NA
Auto-crossover
Enable
1: Enable auto MDI/MDIX
0: Disable auto MDI/MDIX
1
20[5:3]
20.6
Reserved
The default value should be adopted for
normal operation.
R/W 101
NA
NA
Speed10to100en Detect the link partner’s speed change from RW
1
able
10BASE-T to 100BASE-TX by detecting
MLT3 signals
1: Enable
0: Disable
20[8: 7]
20.9
FIFO_Depth
FIFO depth latency
00: latency = 2
01: latency = 3
10: latency = 4
11: latency = 5
RW
10
0
NA
0
MDIX Enable
When disable auto-crossover
RW
0: MDI
1: MDIX
20.10
20.11
Reserved
APS_ON
The default value should be adopted for
normal operation.
R/W
1
1
NA
NA
This bit is used to activate auto power saving RW
(APS) mode
0: Disable APS
1: Enable APS
20[15:12] Reserved
The default value should be adopted for
normal operation.
R/W 0000
NA
Register 21~31 are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
41/48
Dec. 18, 2007
IP1001-DS-R06
Copyright © 2006, IC Plus Corp.
ETC [ ETC ]
