IP1001 LF
Data Sheet
5.3.2
MII Timing
a. Transmit Timing Requirements
Symbol
TTclk1
TTclk1
Ts1
Description
Min.
Typ.
Max.
Unit
Period of transmit clock in 100M mode
Period of transmit clock in 10M mode
TXEN, TXD to TX_CLK setup time
(TXPHASE_SEL=0, no clock delay added)
TXEN, TXD to TX_CLK setup time
(TXPHASE_SEL=1, clock delay added)
TXEN, TXD to TX_CLK hold time
-
-
40
400
-
-
ns
ns
ns
-0.65
3.35
0.2
ns
ns
ns
Th1
(TXPHASE_SEL=0, no clock delay added)
TXEN, TXD to TX_CLK hold time
4.2
(TXPHASE_SEL=1, clock delay added)
TTclk1
MII_TXCLK
Th1
TXEN, TXD[3:0]
Ts1
b. Receive Timing
Symbol
Description
Min.
Typ.
Max.
Unit
TRclk1
TRclk1
Td1
Period of receive clock in 100M mode
Period of receive clock in 10M mode
MII_RXCLK rising edge to RXDV, RXD
(RXPHASE_SEL=0, no clock delay added)
MII_RXCLK rising edge to RXDV, RXD
(RXPHASE_SEL=1, clock delay added)
-
-
40
400
0
-
-
ns
ns
ns
-0.4
0.4
3.6
4
4.4
ns
TRclk1
RX_CLK
Td1
RXDV, RXD[3:0]
44/48
Dec. 18, 2007
IP1001-DS-R06
Copyright © 2006, IC Plus Corp.
ETC [ ETC ]
