IP1001 LF
Data Sheet
5.3.3
GMII Timing
c. Transmit Timing Requirements
Symbol
TTXCLK
Ts2
Description
Min.
Typ.
8
Max.
-
Unit
Period of transmit clock
-
ns
ns
TXEN, TXD to GTX_CLK setup time
(TXPHASE_SEL=0, no clock delay added)
TXEN, TXD to GTX_CLK setup time
(TXPHASE_SEL=1, clock delay added)
TXEN, TXD to GTX_CLK hold time
(TXPHASE_SEL=0, no clock delay added)
TXEN, TXD to GTX_CLK hold time
(TXPHASE_SEL=1, clock delay added)
-0.65
3.35
0.2
ns
ns
ns
Th2
4.2
TTclk2
GTX_CLK
Th2
TXEN, TXD[7:0]
Ts2
d. Receive Timing
Symbol
Description
Min.
-
Typ.
8
Max.
Unit
TRclk2
Td2
Period of receive clock
-
ns
ns
RX_CLK rising edge to RXDV, RXD
(RXPHASE_SEL=0, no clock delay added)
RX_CLK rising edge to RXDV, RXD
(RXPHASE_SEL=1, clock delay added)
0.4
4.4
ns
TRclk2
RX_CLK
Td2
RXDV, RXD[7:0]
45/48
Dec. 18, 2007
IP1001-DS-R06
Copyright © 2006, IC Plus Corp.
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