TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)
Address*
Bit
Name
Function
Reset Default
0x8LPF1
3:0
FRM_MODE[3:0]
Framing Mode.
1011
0000 = nonalign 256 bit.
0001 = CEPT basic frame.
0010 = CEPT with CRC-4 and 100 ms timer.
0011 = CMI.
0100 = CEPT with CRC-4 and 400 ms timer.
0101 = reserved. (Future J2 - G.704.)
0110 = reserved. (Future J2 - NTT Y.)
0111 = reserved.
1000 = nonalign 193 bits.
1001 = SF (FT bits only).
1010 = J-ESF.
1011 = ESF.
1100 = D4.
1101 = J-D4 (SF with Japanese Yellow Alarm).
1110 = DDS.
1111 = SLC-96.
* See Table 429 on page 298 for values of L and P.
Table 435. FRM_ARLR3, Arbiter Link Register 3 (R/W)
This register applies to the transmit path only.
Address* Bit
Name
Function
Reset Default
0x8LPF2 15
FRM_TP_CK_
SRC_EN
Framer Transmit Path Clock Source Enable.
0
0 = FRM_TP_CK_SRC bit is disabled. FRM_SW_TRN
(Table 313 on page 246) bit controls clock source.
1 = FRM_TP_CK_SRC bit is enabled. FRM_SW_TRN bit
is ignored.
Transmit path clock and data is selected with bits
FRM_TP_CK_SRC and FRM_TP_DD_SRC.
14
13
FRM_TP_CK_
SRC
Transmit Path Clock Source.
1
1
0 = transmit clock comes from the frame aligner (transport
applications).
1 = transmit clock comes from the system interface
(switching applications).
FRM_TP_DD_
SRC
Transmit Path Default Data Source.
0 = transmit data comes from the frame aligner (transport
applications).
1 = transmit data comes from the system interface
(switching applications).
12:1
0
RSVD
Reserved. Must write to 0.
0000
FRM_SYSFSM System Frame Sync Mask. A 1 masks the system frame
synchronization signal in the transmit framer formatter.
Note: For those applications that have jitter on the transmit
clock signal relative to the system clock signal,
enable this bit so that the jitter is isolated from the
transmit framer.
* See Table 429 on page 298 for values of L and P.
304
Agere Systems Inc.
ETC [ ETC ]
