RTL8201N
Datasheet
9.2. AC Characteristics
9.2.1. MII Transmission Cycle Timing
Table 33. MII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
t1
TXCLK high pulse width
100Mbps
10Mbps
14
20
26
ns
140
200
260
ns
t2
t3
t4
TXCLK low pulse width
TXCLK period
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
14
140
-
20
200
40
26
ns
ns
ns
ns
ns
260
-
-
-
-
400
24
TXEN, TXD[0:3] setup to
TXCLK rising edge
10
10Mbps
5
-
-
-
ns
ns
t5
TXEN, TXD[0:3] hold after
TXCLK rising edge
100Mbps
10
25
10Mbps
100Mbps
10Mbps
100Mbps
5
-
-
-
-
-
-
ns
ns
ns
ns
t6
t7
TXEN sampled to CRS high
40
-
400
160
TXEN sampled to CRS low
-
10Mbps
-
-
2000
140
ns
ns
t8
t9
Transmit latency
100Mbps
60
70
10Mbps
100Mbps
10Mbps
-
-
-
-
100
-
2000
170
-
ns
ns
ns
Sampled TXEN inactive to end
of frame
Figure 5 and Figure 6 show an example of a packet transfer from MAC to PHY on the MII interface.
t
3
VIH(min)
VIL(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VIL(max)
TXD[0:3]
TXEN
Figure 5. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
t
t
6
7
9
CRS
t
t
8
TPTX+-
Figure 6. MII Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
27
Rev. 1.2
ETC [ ETC ]
