RTL8201N
Datasheet
8.10. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201N is fabricated in a 0.15µm process. The core circuit needs to be powered by 1.5V,
however, the digital IO and DAC circuits need a 3.3V power supply. Two regulators are embedded in the
RTL8201N to convert 3.3V to 1.5V and 1.8V. As with many commercial voltage conversion devices, the
1.5V/1.8V output pin (PWFBOUT) of this circuit requires the use of an output capacitor (22uF tantalum
capacitor) as part of the device frequency compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
8.11. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201N detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201N will start sending this
pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path
has a problem from the point of view of the RTL8201N. The FEFI mechanism is used only in
100Base-FX mode.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
24
Rev. 1.2
ETC [ ETC ]
