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RTL8021N-GR 参数 Datasheet PDF下载

RTL8021N-GR图片预览
型号: RTL8021N-GR
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 40 页 / 606 K
品牌: ETC [ ETC ]
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RTL8201N  
Datasheet  
8.7.3. 10Base-T Transmit & Receive Operation  
10Base-T Transmit  
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial  
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder  
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a  
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data  
stream is shaped by a band-limited filter embedded in the RTL8201N and then transmitted.  
10Base-T Receive  
In 10Base-T receive mode, the Manchester decoder in the RTL8201N converts the Manchester encoded  
data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data  
stream is converted to a parallel 4-bit nibble signal (RXD[0:3]).  
8.8. Repeater Mode Operation  
Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201N into repeater mode. In  
repeater mode, the RTL8201N will assert CRS high only when receiving a packet. In NIC mode, the  
RTL8201N will assert CRS high both when transmitting and receiving packets. If using the RTL8201N in  
a NIC or switch application, set to the default mode. NIC/Switch mode is the default setting and has the  
RPTR pin pulled low, or bit 15 of register 17 is set to 0.  
8.9. Reset, and Transmit Bias  
The RTL8201N can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It  
can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the  
registers and re-initialize them. The media interface will disconnect and restart the auto-  
negotiation/parallel detection process.  
The RTSET pin must be pulled low by a 2Kresister with 1% accuracy to establish an accurate transmit  
bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock  
traces and transmit/receive paths to avoid signal interference.  
Single-Chip/Port 10/100 Fast Ethernet PHYceiver  
With Auto MDIX  
23  
Rev. 1.2  
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