RTL8201N
Datasheet
9.2.2. MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Symbol
Description
Minimum
Typical
20
Maximum
Unit
ns
t1
RXCLK high pulse width
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
14
140
14
26
260
26
200
ns
t2
t3
t4
t5
RXCLK low pulse width
RXCLK period
20
ns
140
-
200
40
260
-
ns
ns
10Mbps
-
400
-
-
-
-
ns
ns
ns
ns
RXER, RXDV, RXD[0:3] setup to 100Mbps
RXCLK rising edge
10
6
-
-
-
10Mbps
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
100Mbps
10
10Mbps
6
-
-
-
-
ns
ns
t6
t7
t8
t9
Receive frame to CRS high
100Mbps
130
10Mbps
100Mbps
10Mbps
-
-
-
-
-
-
-
-
2000
240
ns
ns
ns
ns
End of receive frame to CRS low
1000
150
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
-
-
-
-
3200
120
ns
ns
End of receive frame to sampled
edge of RXDV
100Mbps
10Mbps
-
-
1000
ns
Figure 7 and Figure 8 show an example of a packet transfer from PHY to MAC on the MII interface.
t3
V
RXCLK
IH(min)
IL(max)
V
t1
t2
t4
t5
RXD[0:3]
RXDV
V
V
IH(min)
IL(max)
RXER
Figure 7. MII Reception Cycle Timing-1
RXCLK
RXDV
t9
t8
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 8. MII Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
28
Rev. 1.2
ETC [ ETC ]
