RTL8201N
Datasheet
9.2.3. RMII Timing
Table 35. RMII Timing
Description
Minimum
Typical
Maximum
Unit
REFCLK period
-
20
-
-
-
ns
ns
TXEN, TXD[0:1], CRSDV, RXD[0:1], RXER
setup to REFCLK rising edge
4
TXEN, TXD[0:1], CRSDV, RXD[0:1], RXER
hold after REFCLK rising edge
2
-
-
ns
9.2.4. SNI Transmission Cycle Timing
Table 36. SNI Transmission Cycle Timing
Symbol Description
Minimum
Maximum
Unit
ns
t1
TXCLK high pulse width
TXCLK low pulse width
36
36
80
20
10
-
-
-
t2
t3
t4
t5
t8
ns
TXCLK period
120
-
ns
TXEN, TXD0 setup to TXCLK rising edge
TXEN, TXD0 hold after TXCLK rising edge
Transmit latency
ns
-
ns
50
ns
Figure 9 and Figure 10 show an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
TXCLK
V
IL(max)
t1
t2
t5
t4
V
V
TXD0
TXEN
IH(min)
IL(max)
Figure 9. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t8
t9
TPTX+-
Figure 10. SNI Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
29
Rev. 1.2
ETC [ ETC ]
