RTL8201N
Datasheet
9.2.5. SNI Reception Cycle Timing
Table 37. SNI Reception Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
t7
t8
RXCLK high pulse width
RXCLK low pulse width
RXCLK period
36
36
80
40
40
-
-
-
-
-
ns
-
120
-
ns
RXD0 setup to RXCLK rising edge
RXD0 hold after RXCLK rising edge
Receive frame to CRS high
End of receive frame to CRS low
Decoder acquisition time
-
ns
-
-
-
ns
50
160
1800
ns
-
-
ns
-
600
ns
Figure 11 and Figure 12 show an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
RXCLK
V
IL(max)
t2
t1
t4
t5
V
V
RXD0
IH(min)
IL(max)
Figure 11. SNI Reception Cycle Timing-1
RXCLK
RXD0
t8
t6
t7
CRS
TPRX+-
Figure 12. SNI Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
30
Rev. 1.2
ETC [ ETC ]
