Proprietary TranSwitch Corporation Information for use Solely by its Customers
L3M
TXC-03452B
DATA SHEET
MEMORY MAP
Please note that all control registers (C0H to CAH) and the FIFO Leak Rate Register (A0H) must be initialized
to 00H value unless otherwise specified below or required by the application.
CONTROL BITS
Address
(Hex)
Mode*
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TUG3
STS3
DPOS1
INVCI
DPOS0
INVCO
APOS1
RING
APOS0
FLBK
INTZ
TEST
L3LBK
ADDZ
EXC2
DS3
SLBK
L3Z
DECODE
CODE
ALM2AIS ALM2FB9 TLAISGN TPAISGN TPAIS00
EXZ5
EXOO
COR
EXZ4
FEBE9EN RAMRDI
TEST
EXZ3
EXH4
EXF2
EXG1
TEST
EXJ1
FEBEEN XALM2AIS
TLOC2AIS TLOS2AIS
DROPT POH2RAM RAISGN RAISEN WGDEC
PSL2AIS
RPRBS
FASTPTR TOHOUT
H4CTR
TEST
PAT23
DIV4
ENANA
TXANA
TPRBS
RXRST
TESTB3
FIXPTR
INVCTRL TXRST
RESETC
C2 Compare
TEST
NOPOH
RDI5
FEBEBLK
TEST
TEST
STATUS BITS
Address
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Hex)**
B0
B1
B2
B3
B4
B5
B6
B7
R
R/W(L)
R
DLOC
DLOC
RDI
DLOJ1
DLOJ1
L3LOS
L3LOS
FEBE9
FEBE9
LOVFL
LOVFL
BUSERR
BUSERR
L3LOC
L3LOC
NEW
E1AIS
E1AIS
TOVFL
TOVFL
LOP
LOP
PAIS
PAIS
PSLERR
PSLERR
ALOC
C2EQ0
C2EQ0
ALOJ1
ALOJ1
XPAIS
XPAIS
OOL
L3AIS
L3AIS
RAMLOC
RAMLOC
XSTAI
R/W(L)
R
RDI
ALOC
SINT
TUG3NEW ROVFL
TUG3NEW ROVFL
XISTAT
XISTAT
RPLOC
RPLOC
R/W(L) Reserved
NEW
XSTAI
R
L3ERR
L3ERR
RFRST
RFRST
TFRST VCXOLOC TPLOC
TFRST VCXOLOC TPLOC
R/W(L)
OOL
*R/W: Read/write; R: Read only; R/W(L): Read/Write - latched register.
**Even addresses contain unlatched status bits. Odd addresses contain latched status bits.
INTERRUPT MASK BITS
Address
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Hex)
BA
BB
BC
BD
R/W
R/W
R/W
R/W
DLOC
RDI
DLOJ1
L3LOS
FEBE9
LOVFL
BUSERR
L3LOC
NEW
E1AIS
TOVFL
LOP
PAIS
RAMLOC
XSTAI
PSLERR
ALOC
C2EQ0
ALOJ1
XPAIS
OOL
L3AIS
HINT
TUG3NEW ROVFL
XISTAT
RPLOC
L3ERR
RFRST
TFRST VCXOLOC TPLOC
TXC-03452B-MB
Ed. 6, April 2001
- 61 of 96 -
ETC [ ETC ]
