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L3M
TXC-03452B
DATA SHEET
LINE INTERFACE
144-Lead 208-Lead
QFP BGA
Lead No. Lead No.
Symbol
I/O/P
Type
Name/Function
RNRZD
92
H13
O
CMOS Receive Line NRZ Data: Output provided for an optional
4mA
external performance monitoring circuit. This serial NRZ
output is provided after the decoder (transmit direction),
independent of whether the input is NRZ or rail. Data is
always clocked out on positive transitions of clock
(RNRZC). This lead goes to a high impedance state when
control bit L3Z is set to 1.
RNRZC
TPOS
93
H14
C14
A15
O
I
CMOS Receive Line Clock: NRZ data on lead RNRZD is clocked
4mA
out of the L3M device on positive transitions of this clock.
This lead goes to a high impedance state when control bit
L3Z is set to 1.
109
110
CMOS Transmit NRZ Line Data/Positive Rail Data: Serial NRZ
input for the 44.736 or 34.368 Mbit/s asynchronous line
data. This lead also provides the positive rail data input for
an internal decoder.
TNEG/
LOS
I
CMOS Transmit Negative Rail Data: When operating in the P/N
rail mode, this lead provides a negative rail input for the
internal decoder. When operating in the NRZ mode, a high
on this lead instead indicates an external loss of signal
alarm, so that the lead must be tied to ground if it is not
used for input of an external loss of signal indication.
TCLK
RCLK
111
142
A14
I
CMOS Transmit Line Clock: NRZ or rail data is clocked into the
L3M device using the TPOS/TNEG signal leads on positive
transitions of this clock when control bit INVCI is set to 0.
NRZ or rail data is clocked in on negative transitions when
control bit INVCI is set to 1. TCLK is used as the input clock
for the transmit PRBS generator and it must be present to
generate a test pattern.
B3
O
CMOS Receive Line Clock: Line data present on the RPOS/
4mA
RNEG signal leads (44.736 or 34.368 Mbit/s) is clocked out
of the L3M device on negative transitions of this clock when
control bit INVCO is set to 0. NRZ or rail data is clocked out
on positive transitions of this clock when control bit INVCO
is set to 1. This lead goes to a high impedance state when
control bit L3Z is set to 1.
RPOS
RNEG
143
144
A2
A1
O
O
CMOS Receive Line NRZ Data/Positive Rail Data: Serial NRZ
4mA
output for the 44.736 or 34.368 Mbit/s asynchronous line
data. This lead also provides the positive rail output when
the rail interface is selected. This lead goes to a high
impedance state when control bit L3Z is set to 1.
CMOS Receive Negative Rail Data: This lead provides a negative
4mA
rail interface from the internal coder. This lead goes to a
high impedance state when control bit L3Z is set to 1. When
the NRZ interface is selected, this lead outputs a 0.
TXC-03452B-MB
Ed. 6, April 2001
- 14 of 96 -
ETC [ ETC ]
