4. Serial data register L (SDRL)
Bit
7
6
5
4
3
2
1
0
SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO1 pin in LSB-first order. In the
replacement process, data is input LSB-first from the SI1 pin, and the data is shifted in the MSB →
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
1
1
1
1
1
1
1
Initial value
Read/Write
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.
259
ETC [ ETC ]
