Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0)
When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock
cycle.
Serial Clock Cycle
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Prescaler Division Ratio
ø = 2.5 MHz
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ø/1024 (initial value)
ø/256
ø/64
ø/32
ø/16
ø/8
3.2 µs
ø/4
1.6 µs
øW/4
122 µs
2. Serial control status register 1 (SCSR1)
Bit
7
—
1
6
5
4
—
1
3
—
1
2
—
1
1
MTRF
0
0
SOL
0
ORER
0
STF
0
Initial value
Read/Write
—
R/W
R/(W)*
—
—
—
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit register that indicates the operational and error status of SCI1.
Upon reset, SCSR1 is initialized to H'9C.
Bit 7: Reserved bit
Bits 7 is reserved; it is always read as 1 and cannot be modified.
256
ETC [ ETC ]
